Im16) || 00Later in lecture: higher-level connection between mux and branch condAdrInstMemoryAdderAdderPCClk00Mux4nPC_MUX_selPC ... 哪腔磐备炼Lecture 6Designing Single Cycle ControlStart X:40..PAGE:2Recap: A Single Cycle DatapathRs, Rt, Rd and ... *The result of the last lecture is this single-cycle datapath.+1 = 6 min.