_1164.all; use ieee.std_logic_unsigned.all; entity key is port( clk : in std_logic; key_0,key_1,key_2, ... x3 : buffer integer range 0 to 9; y1,y2,y3 : buffer integer range 0 to 9; data : buffer integer range ... key_5,key_6,key_7,key_8,key_9 : in std_logic; key_a,key_b,key_c,key_d,key_e,key_f : in std_logic; x1,x2,