Semiconductor Device and Design - 8_

목차

1. CMOS process design rules
2. The method of implementing the half-adder
3. Layout of the full-adder cell
4. parasitic circuit

본문내용

■ Cmos design rules : The physical mask layout of any circuit to be manufacture using a particular process. It must conform to a set of geometric constraints or rules, which are generally called layout design rules. The main objective of design rules is to achieve

참고 자료

Basic Electronics for Scientists and Engineers : Dennis L. Eggleston
https://www.elprocus.com/half-adder-and-full-adder/
http://blog.naver.com/PostView.nhn?blogId=jis2312&logNo=221295181241&parentCategoryNo=&categoryNo=14&viewDate=&isShowPopularPosts=true&from=search
https://www.researchgate.net/figure/Bipolar-process-overview-of-device-type-B-with-deposited-and-wet-etched-silicon-nitride_fig2_226216054
https://techweb.rohm.co.kr/knowledge/si/s-si/03-s-si/4873