연세대학교 기초디지털실험 2주차 예비레포트 (basic of verilog)
- 최초 등록일
- 2021.08.18
- 최종 저작일
- 2020.09
- 5페이지/ 어도비 PDF
- 가격 1,500원
목차
Ⅰ. Research on theory
1. adder
2. 2’s complement & Subtractor
Ⅱ. About verilog HDL
Ⅲ. What do we learn from the experiment 2
Ⅳ. Reference
본문내용
1. adder
Adder is a digital circuit that does addition operations.
Half adder has 2 inputs A, B and it produces 2 outputs ‘carry out’ and ‘sum’. This performs an operation that adds two binary numbers, whose logic gate can be seen in pic 1. Take XOR to make sum and apply AND gate to two inputs to make carry out. The truth table for half adder is in pic2.
Full adder has three inputs, A, B, carry in and generate two outputs of carry out and sum. The logic gate and the truth table of full adder follows pic3 and pic4, respectively and can be represented by :
Full adder can hold a carry bit from previous operation result, so binary adder can be implemented with full adder. For example, 4-bit adder can be implemented by adding 4 FAs together. Its diagram is shown pic5.
참고 자료
Yonsei univ. Electrical Electronic Engineering - Week 2 Lecture: Basic of Verilog
Charles H. Roth, Jr.& Larry L Kinney. (2013). Fundamentals of Logic Design.
Cengage Learning.