연세대학교 기초디지털실험 1주차 결과레포트

목차

Ⅰ. Object

Ⅱ. Research on theory
1. Design Source Add & Creation
2. Simulation Source Add & Creation
3. Test Benchmark Description for Simulation
4. Module Define
5. Module Instantiation & Module Connection
6. Pin Assignment & Connection to Top Module

Ⅲ. Waveform simulation results
1. Logic Gate Circuit
2. Verilog Circuit Design : 2-bit adder

Ⅳ. FPGA results
1. Logic Gate Circuit
2. Verilog Circuit Design : 2-bit adder

Ⅴ. Discussion

Ⅵ. Reference

본문내용

Ⅰ. Object
This lecture is about understanding the fundamental theory of Verilog and then implementing and testing the logic circuit by simulation waveform and PYNQ board.

Ⅱ. Research on theory
A digital logic circuit does operation with binary signals, 0 and 1. There are various kinds of gate such as AND, OR, NOT and XOR. FPGA, Field Programmable Gate Array is an integrated circuit designed to be constructed by a customer after manufacture. HDL, Hardware Description Language, helps implementing circuit schematics and designating modules’ behavior.
Modules are the most basic units of design. They are connecting to each other using ports. Instance, which is made up of name, variable, parameter and ports, is defined by module. Signals can be declared like reg, wire. When writing number, it should be written in order of size, ‘, base, number, like 2’b11.

1. Design Source Add & Creation
After creating project in right path, we should make specific logic gate and the entire block

참고 자료

Yonsei univ. Electrical Electronic Engineering - Week 1 lecture : how to start