베릴로그 verilog 프로젝트project 기본 전자시계 digital watch 소스 파일
- 최초 등록일
- 2013.09.09
- 최종 저작일
- 2012.09
- 66페이지/
MS 워드
- 가격 10,000원
목차
없음
본문내용
NET "in_CLK" LOC = P76;
NET "out_En" LOC = P154;
NET "out_RS" LOC = P156;
NET "out_RW" LOC = P155;
NET "out_DB[7]" LOC = P143;
NET "out_DB[6]" LOC = P144;
NET "out_DB[5]" LOC = P146;
NET "out_DB[4]" LOC = P147;
NET "out_DB[3]" LOC = P148;
NET "out_DB[2]" LOC = P149;
NET "out_DB[1]" LOC = P150;
NET "out_DB[0]" LOC = P152;
NET "in_AMPM" LOC = P71;
NET "in_hr_UP" LOC = P63;
NET "in_hr_DOWN" LOC = P68;
NET "in_min_UP" LOC = P67;
NET "in_sec_UP" LOC = P65;
NET "in_min_DOWN" LOC = P74;
NET "in_sec_DOWN" LOC = P50;
NET "in_MODE" LOC = P58;
# PlanAhead Generated physical constraints
NET "in_24" LOC = P64;
NET "in_RESET" LOC = P45;
`timescale 1ns / 1ps
module digital_clock_jokyo(out_En, out_RS, out_RW, out_DB, in_CLK,
in_MODE, in_sec_UP, in_sec_DOWN, in_min_UP,in_min_DOWN,
in_hr_UP, in_hr_DOWN, in_AMPM, in_24, in_RESET);
output reg out_En, out_RS, out_RW;
output reg [7:0]out_DB;
input in_CLK;
input in_MODE;
input in_sec_UP, in_sec_DOWN, in_min_UP, in_min_DOWN, in_hr_UP, in_hr_DOWN, in_AMPM, in_24, in_RESET;
reg reg_RS, reg_RW;
reg reg_Initial; // 초기화 했는지 기억하는 변수
reg reg_Inst_Start; // 명령 push 시작 변수
reg reg_sec_01, reg_sec_10, reg2_sec_10, reg_min_01, reg2_min_01;
reg reg_min_10, reg2_min_10, reg_hr_01, reg2_hr_01, reg_hr_10, reg2_hr_10;
reg reg_ampm, reg2_ampm, reg3_ampm;
reg reg_ampm2, reg2_ampm2 ;
참고 자료
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