verilog 로 구현한 Pipelined Direct Form FIR Filter , bit serial 곱셈기
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Pipelined Direct Form FIR Filter 와 bit serial 곱셈기 입니다.verilog 로 구현하였으며
보고서랑 verilog 코드 포함되어있습니다.
목차
1. Bit - serial 8x8 multipiler1) Verilog code
2) waveform
3)Synthesis result
4) 비교
2. Pipelined Direct Form FIR Filter
1) Verilog code
2) waveform
3)Synthesis result
4) 비교
본문내용
1. Bit - serial 8x8 multipiler1) Verilog code
module w_8input( w, a, clk, reset);
input [7:0] a;
input clk, reset;
output [7:0] w;
Dff U00_Dff( w[0], a[0], clk, reset);
Dff U01_Dff( w[1], a[1], clk, reset);
Dff U02_Dff( w[2], a[2], clk, reset);
Dff U03_Dff( w[3], a[3], clk, reset);
Dff U04_Dff( w[4], a[4], clk, reset);
Dff U05_Dff( w[5], a[5], clk, reset);
Dff U06_Dff( w[6], a[6], clk, reset);
Dff U07_Dff( w[7], a[7], clk, reset);
endmodule
module w_3input( w, a, clk, reset);
input [2:0] a;
input clk, reset;
output [2:0] w;
Dff U00_Dff( w[0], a[0], clk, reset);
Dff U01_Dff( w[1], a[1], clk, reset);
Dff U02_Dff( w[2], a[2], clk, reset);
endmodule
module w_16output( z, wz, clk, reset);
input [15:0] wz;
input clk, reset;
output [15:0] z;
Dff U00_Dff( z[0], wz[0], clk, reset);
Dff U01_Dff( z[1], wz[1], clk, reset);
Dff U02_Dff( z[2], wz[2], clk, reset);
Dff U03_Dff( z[3], wz[3], clk, reset);
Dff U04_Dff( z[4], wz[4], clk, reset);
Dff U05_Dff( z[5], wz[5], clk, reset);
Dff U06_Dff( z[6], wz[6], clk, reset);
Dff U07_Dff( z[7], wz[7], clk, reset);
Dff U08_Dff( z[8], wz[8], clk, reset);
Dff U09_Dff( z[9], wz[9], clk, reset);
Dff U10_Dff( z[10], wz[10], clk, reset);
Dff U11_Dff( z[11], wz[11], clk, reset);
Dff U12_Dff( z[12], wz[12], clk, reset);
Dff U13_Dff( z[13], wz[13], clk, reset);
Dff U14_Dff( z[14], wz[14], clk, reset);
Dff U15_Dff( z[15], wz[15], clk, reset);
endmodule
wiring.v
wiring.v - DFF 과 wiring 하기위해 만들었다
w_8input 은 입력단에서 w_3input 은 counter 와 먹스 switch 사이에, w_16output 은 output 단에서 사용된다.
참고 자료
없음압축파일 내 파일목록
P11.hwp
bitsirial/bit_out.txt
bitsirial/bit_top.v
bitsirial/counter.v
bitsirial/Dff.v
bitsirial/input1_in_hex.txt
bitsirial/input2_in_hex.txt
bitsirial/mux5to1.v
bitsirial/output_in_hex.txt
bitsirial/stimul.v
bitsirial/verify_out.txt
bitsirial/wiring.v
pipe/Dff.v
pipe/filt_coeff.txt
pipe/input_vector.txt
pipe/output_vector_hex.txt
pipe/PIPE_out.txt
pipe/stimul.v
pipe/sub.v
pipe/top.v
pipe/verify_out.txt
pipe/wiring.v
bitsirial/bit_out.txt
bitsirial/bit_top.v
bitsirial/counter.v
bitsirial/Dff.v
bitsirial/input1_in_hex.txt
bitsirial/input2_in_hex.txt
bitsirial/mux5to1.v
bitsirial/output_in_hex.txt
bitsirial/stimul.v
bitsirial/verify_out.txt
bitsirial/wiring.v
pipe/Dff.v
pipe/filt_coeff.txt
pipe/input_vector.txt
pipe/output_vector_hex.txt
pipe/PIPE_out.txt
pipe/stimul.v
pipe/sub.v
pipe/top.v
pipe/verify_out.txt
pipe/wiring.v