Verilog HDL로 짠 NRZ-to-Manchester 분석
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한컴오피스
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Verilog HDL로 짠 NRZ-to-Manchester 분석
목차
< NRZ to Manchester Coding - Self >
1. Mealy type
2. Moore type
< NRZ to Manchester Coding - chapter 6 >
1. Mealy type
2. Moore type
본문내용
4) VerilogHDL Coding
① Source Code
`timescale 1ns / 1ps
module nrz_to_m_mealy(B_in, clk, reset, q1, q2, B_out);
input B_in;
input clk;
input reset;
output q1;
output q2;
output B_out;
reg q1,q2;
reg next_q1, next_q2;
assign B_out = (~q1)|((~q2)&reset&B_in);
always @(negedge clk) begin
if(q1 == 0 || q1 == 1) begin
q1 = next_q1;
q2 = next_q2;
end
else begin
q1 = 0;
q2 = 0;
end
end
always @(B_in or reset or q1 or q2) begin
next_q1 = (~q1)|q2|(reset&B_in);
next_q2 = (~q2)&q1&reset;
end
endmodule
② Test Bench Code
`timescale 1ns / 1ps
module tb_nrz_to_m_mealy_v;
// Inputs
reg B_in;
reg clk;
reg reset;
// Outputs
wire q1;
wire q2;
wire B_out;
// Instantiate the Unit Under Test (UUT)
nrz_to_m_mealy uut (.B_in(B_in), .clk(clk), .reset(reset), .q1(q1), .q2(q2), .B_out(B_out));
initial begin
// Initialize Inputs
clk = 1`b0;
forever #10 clk = ~clk;
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