비교기 Verilog source code & test bench code

컴파일 실행환경

Quartus2, ModelSim, Altera DE2 Board

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db/lab2.(0).cnf.cdb
db/lab2.(0).cnf.hdb
db/lab2.(1).cnf.cdb
db/lab2.(1).cnf.hdb
db/lab2.(2).cnf.cdb
db/lab2.(2).cnf.hdb
db/lab2.(3).cnf.cdb
db/lab2.(3).cnf.hdb
db/lab2.asm.qmsg
db/lab2.asm.rdb
db/lab2.asm_labs.ddb
db/lab2.cbx.xml
db/lab2.cmp.bpm
db/lab2.cmp.cdb
db/lab2.cmp.hdb
db/lab2.cmp.idb
db/lab2.cmp.kpt
db/lab2.cmp.logdb
db/lab2.cmp.rdb
db/lab2.cmp0.ddb
db/lab2.cmp1.ddb
db/lab2.cmp_merge.kpt
db/lab2.db_info
db/lab2.eda.qmsg
db/lab2.fit.qmsg
db/lab2.hier_info
db/lab2.hif
db/lab2.ipinfo
db/lab2.lpc.html
db/lab2.lpc.rdb
db/lab2.lpc.txt
db/lab2.map.bpm
db/lab2.map.cdb
db/lab2.map.hdb
db/lab2.map.kpt
db/lab2.map.logdb
db/lab2.map.qmsg
db/lab2.map.rdb
db/lab2.map_bb.cdb
db/lab2.map_bb.hdb
db/lab2.map_bb.logdb
db/lab2.pre_map.cdb
db/lab2.pre_map.hdb
db/lab2.qns
db/lab2.root_partition.map.reg_db.cdb
db/lab2.routing.rdb
db/lab2.rpp.qmsg
db/lab2.rtlv.hdb
db/lab2.rtlv_sg.cdb
db/lab2.rtlv_sg_swap.cdb
db/lab2.sas
db/lab2.sgate.rvd
db/lab2.sgate_sm.rvd
db/lab2.sgdiff.cdb
db/lab2.sgdiff.hdb
db/lab2.sld_design_entry.sci
db/lab2.sld_design_entry_dsc.sci
db/lab2.smart_action.txt
db/lab2.sta.qmsg
db/lab2.sta.rdb
db/lab2.sta_cmp.6_slow.tdb
db/lab2.syn_hier_info
db/lab2.tis_db_list.ddb
db/lab2.tmw_info
db/lab2.vpr.ammdb
db/logic_util_heursitic.dat
db/prev_cmp_lab2.qmsg
incremental_db/compiled_partitions/lab2.db_info
incremental_db/compiled_partitions/lab2.root_partition.cmp.ammdb
incremental_db/compiled_partitions/lab2.root_partition.cmp.cdb
incremental_db/compiled_partitions/lab2.root_partition.cmp.dfp
incremental_db/compiled_partitions/lab2.root_partition.cmp.hdb
incremental_db/compiled_partitions/lab2.root_partition.cmp.kpt
incremental_db/compiled_partitions/lab2.root_partition.cmp.logdb
incremental_db/compiled_partitions/lab2.root_partition.cmp.rcfdb
incremental_db/compiled_partitions/lab2.root_partition.map.cdb
incremental_db/compiled_partitions/lab2.root_partition.map.dpi
incremental_db/compiled_partitions/lab2.root_partition.map.hbdb.cdb
incremental_db/compiled_partitions/lab2.root_partition.map.hbdb.hb_info
incremental_db/compiled_partitions/lab2.root_partition.map.hbdb.hdb
incremental_db/compiled_partitions/lab2.root_partition.map.hbdb.sig
incremental_db/compiled_partitions/lab2.root_partition.map.hdb
incremental_db/compiled_partitions/lab2.root_partition.map.kpt
incremental_db/README
output_files/lab2.asm.rpt
output_files/lab2.done
output_files/lab2.eda.rpt
output_files/lab2.fit.rpt
output_files/lab2.fit.smsg
output_files/lab2.fit.summary
output_files/lab2.flow.rpt
output_files/lab2.jdi
output_files/lab2.map.rpt
output_files/lab2.map.summary
output_files/lab2.pin
output_files/lab2.pof
output_files/lab2.sof
output_files/lab2.sta.rpt
output_files/lab2.sta.summary
simulation/modelsim/rtl_work/_temp/
simulation/modelsim/rtl_work/comparators/_primary.dat
simulation/modelsim/rtl_work/comparators/_primary.dbs
simulation/modelsim/rtl_work/comparators/_primary.vhd
simulation/modelsim/rtl_work/comparators/verilog.prw
simulation/modelsim/rtl_work/comparators/verilog.psm
simulation/modelsim/rtl_work/lab2/_primary.dat
simulation/modelsim/rtl_work/lab2/_primary.dbs
simulation/modelsim/rtl_work/lab2/_primary.vhd
simulation/modelsim/rtl_work/lab2/verilog.prw
simulation/modelsim/rtl_work/lab2/verilog.psm
simulation/modelsim/rtl_work/mux/_primary.dat
simulation/modelsim/rtl_work/mux/_primary.dbs
simulation/modelsim/rtl_work/mux/_primary.vhd
simulation/modelsim/rtl_work/mux/verilog.prw
simulation/modelsim/rtl_work/mux/verilog.psm
simulation/modelsim/rtl_work/seg/_primary.dat
simulation/modelsim/rtl_work/seg/_primary.dbs
simulation/modelsim/rtl_work/seg/_primary.vhd
simulation/modelsim/rtl_work/seg/verilog.prw
simulation/modelsim/rtl_work/seg/verilog.psm
simulation/modelsim/rtl_work/tb_lab2/_primary.dat
simulation/modelsim/rtl_work/tb_lab2/_primary.dbs
simulation/modelsim/rtl_work/tb_lab2/_primary.vhd
simulation/modelsim/rtl_work/tb_lab2/verilog.prw
simulation/modelsim/rtl_work/tb_lab2/verilog.psm
simulation/modelsim/rtl_work/_info
simulation/modelsim/rtl_work/_vmake
simulation/modelsim/lab2.sft
simulation/modelsim/lab2.vo
simulation/modelsim/lab2_fast.vo
simulation/modelsim/lab2_modelsim.xrf
simulation/modelsim/lab2_run_msim_rtl_verilog.do
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak1
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak10
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak11
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak2
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak3
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak4
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak5
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak6
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak7
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak8
simulation/modelsim/lab2_run_msim_rtl_verilog.do.bak9
simulation/modelsim/lab2_v.sdo
simulation/modelsim/lab2_v_fast.sdo
simulation/modelsim/modelsim.ini
simulation/modelsim/msim_transcript
simulation/modelsim/vsim.wlf
lab2.jdi
lab2.qpf
lab2.qsf
lab2.qsf.bak
lab2.qws
lab2.v
lab2.v.bak
lab2_nativelink_simulation.rpt
tb_lab2.v
tb_lab2.v.bak

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